The use of MOS floating gate storage devices in semiconductor memories has increased rapidly in recent years. A typical MOS floating gate storage device includes a floating gate structure disposed over the surface of a semiconductor substrate between spaced-apart source and drain regions. A control gate is then vertically aligned with the floating gate. Programming of the storage device is carried out by applying a potential to the control gate such that charge carriers are transported between the semiconductor substrate and the floating gate, whereupon the threshold voltage in the channel region established between the spaced-apart source and drain regions is modified. During read operations, the presence or absence of charge carriers on the floating gate can be determined by simply measuring the presence or absence of current flow through the channel region in response to voltage potentials applied to the drain region. When floating gate storage devices of the type described above are incorporated in a semiconductor memory array, individual floating gates are utilized for each storage device while a single conductive strip is generally etched to define the control gates for all of the storage devices in a single memory array row. This single conductive strip is commonly known as a word line. The memory array is prepared for programming or read operations by enabling the word line of a particular memory array row using a unique x-address applied to the address inputs of the memory array.
During manufacture of the memory array, defects in various storage devices positioned along one or more rows in the memory array may occur, giving rise to erroneous data read-outs when the word line connected to the defective storage devices is addressed. In order to salvage memory arrays having such faulty word lines, semiconductor manufacturers often construct memory arrays with several additional or redundant rows of storage devices, each redundant row being tied to a redundant word line. If a faulty word line is located during quality control examination of the memory array, the x-address of the faulty word line is programmed into an enabling circuit for one of the redundant word lines. Thereafter, whenever the faulty word line is addressed, the redundant word line will instead be enabled.
It can thus be seen that the presence of redundant word lines in a semiconductor memory array significantly increases the manufacturing yield from any batch of memory arrays undergoing simultaneous construction. Despite the increased manufacturing yields attainable with redundant row techniques, however, economic and engineering constraints dictate a finite limit on the number of redundant word lines which can practically be provided for any given memory array. Hence, a distinct possibility exists that the number of defective storage devices in a given memory array will exceed the back-up memory capacity of that array, i.e., the possibility exists that the number of faulty word lines in the array will be greater than the number of redundant word lines associated with the array. In the latter event, of course, the array is rendered useless unless some additional means for programming the faulty word lines out of the array can be found.